More technical details of the AMD 3D stacking technologies Zen3 have been announced. Officials claim that it can bring a 15% increase in-game performance. In the Hot Chips 33 demonstration, AMD outlined the future of 3D stacking technology. For example, AMD stated that they chose a micro bump (μbump) pitch of 9 microns, which is denser than the future Intel Foveros Direct technology of 10 microns.
AMD showcased existing and future 3D stacking technology. As the amount of TSV (Through Silicon Via) bonding increases between vertical wafers or between chips, the technology will focus on more complex 3D stacking designs. Allegedly, stacking allows full-mode-to-die stacking, bringing the effect of having DRAM on the CPU or CPU on the CPU. The development direction of this technology is to put independent modules on their own modules, just like core + core.
Ultimately, the spacing of TSVs will become denser, so that module splitting, folding and even circuit splitting is possible, which will completely change the future of the processor as we know it today. AMD has also listed all existing stacking technologies, including Intel’s fooveros/EMIB technology, which means that AMD is considering using this technology in its processors.
AMD expects its 3D chip stacking technology to provide 3 times the interconnect energy efficiency and 15 times the interconnect density. In addition, AMD also announced a new generation of AMD Zen3 CPU 3D chipset plan, the chipset will use core-to-core TSV.
It is reported that this technology will increase the L3 cache by another 64MB, and AMD has previously demonstrated the potential of its 3D V-Cache technology on the AMD Ryzen 9 5900X CPU (32+64MB L3 cache). AMD revealed that this design increases the game frame rate by 15%.
In addition, AMD announced that it will mass-produce Ryzen CPUs equipped with 3D V-Cache before the end of this year.
