Last week, Gigabyte was attacked by hackers, and 112GB of data has since been leaked, including information about AMD’s next-generation EPYC processor (code-named Genoa). In other words, these chips will have a 96-core design, support 12-channel DDR5 memory, and introduce AVX-512 instruction set support for the AMD lineup for the first time.
AVX-512 (Advanced Vector Extension 512) is a 512-bit extension of the 256-bit Advanced Vector Extensions SIMD instruction for the x86 instruction set architecture proposed by Intel in July 2013 and is used in Intel’s Xeon Phi x200 It can be implemented in Skylake-X CPU to accelerate the performance of workloads and use cases, such as scientific simulation, financial analysis, artificial intelligence (AI)/deep learning, 3D modeling and analysis, image and audio/video processing, cryptography and data Compression, etc.
However, due to the significant impact on performance after AVX-512 is turned on, Intel’s 12th-generation processor Alder Lake will cancel support for AVX-512 instruction set support. AMD Ryzen 6000 series processors will be the first to support DDR5 memory and will use the AM5 chipset based on the LGA1718 socket and a new IHS design. It is expected to be unveiled in the second or third quarter of next year.